Le vendredi 05 juillet 2013 à 17:12 +0200, Johannes Pfeifer a écrit :
can anyone tell me what is wrong with this mod-file?
The error message in sim1 is: Attempted to access x(0,1); index must be a positive integer or logical.
It seems as if for simul the preprocessor is not correctly transforming the model to have just one lead or lag as we are accessing x(it_ - 2). Using stoch_simul in contrast works.
In deterministic mode, Dynare does *not* transform the exogenous with leads or lags > 2. This would increase the size of the model for no benefit.
The bug was in sim1.m (which is executed with simul and stack_solve_algo=0, i.e. the default value). The code was not taking into account the fact that lags on exogenous can be > 1. I just pushed a fix. Other values of stack_solve_algo (in particular the value 6, which is the historical LBJ algorithm) are normally not affected. I am surprised that we did not realize this problem before; I guess people are not yet aware that they can use lags on exogenous variables.
Your MOD file now fails differently (no convergence), but I guess this is a model stability issue.